Cypress Semiconductor /psoc63 /CPUSS /CM4_PWR_CTL

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Interpret as CM4_PWR_CTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (OFF)PWR_MODE 0VECTKEYSTAT

PWR_MODE=OFF

Description

CM4 power control

Fields

PWR_MODE

Set Power mode for CM4

0 (OFF): Switch CM4 off Power off, clock off, isolate, reset and no retain.

1 (RESET): Reset CM4 Clock off, no isolated, no retain and reset.

Note: The CM4 CPU has a AIRCR.SYSRESETREQ register field that allows the CM4 to reset the complete device (RESET only resets the CM4), resulting in a warm boot.

2 (RETAINED): Put CM4 in Retained mode This can only become effective if CM4 is in SleepDeep mode. Check PWR_DONE flag to see if CM4 RETAINED state has been reached. Power off, clock off, isolate, no reset and retain.

3 (ENABLED): Switch CM4 on. Power on, clock on, no isolate, no reset and no retain.

VECTKEYSTAT

Register key (to prevent accidental writes).

  • Should be written with a 0x05fa key value for the write to take effect.
  • Always reads as 0xfa05.

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